This invention generally relates to formation of an alignment mark, and more particularly relates to a method for forming an alignment mark which is employed in the process of manufacturing a silicon semiconductor device, especially in the process of forming a microscopic electronic structure on the surface of a semiconductor or silicon substrate. The invention also relates to a method for forming a structure covering the alignment mark for protection thereof.
In the process of manufacturing a semiconductor device, the photolithographic process is generally employed to process a desired microscopic semiconductor structure on a semiconductor or silicon substrate surface. This photolithographic process typically consists of the steps of forming a photoresist film to cover the silicon substrate surface; projecting the light on the photoresist film to focus a predetermined light pattern thereon with help of an optical projector; developing in part the photoresist film exposed to the light; removing the remaining photoresist film unexposed to the light; and etching the semiconductor substrate surface portion as revealed by removing the photoresist film until the desired pattern protected by the photoresist is appreciably obtained. This photolithographic process is repetitively performed using several different patterns until the desired microscopic semiconductor structure is completed on the semiconductor substrate surface. Therefore, in the photolithographic process, it is strictly required to accurately align the pattern previously formed on the substrate with a pattern which is to be formed next thereon. In other words, the photolithographic process requires a so-called precise alignment process for aligning one pattern with the next. In order to accurately carry out this process, some marks are employed as alignment marks which are provided in predetermined positions on the substrate surface, and relative positioning between patterns is performed referring to these marks.
Typically, formation of these marks may be simultaneously executed in parallel with other processes such as a process for forming an electrical wiring over the substrate. This process will now be described with reference to FIGS. 4 and 5 showing a prior art method in which formation of the alignment mark is carried out in parallel with formation of an aluminum wiring over the substrate. At first, a silicon oxide film layer 12 is formed to cover the surface of a silicon substrate 10. While some holes for use in the aluminum wiring are bored by etching the oxide film layer 12 with a suitable etchant, formation of recesses 14 is carried out by etching the oxide film 12 at predetermined positions where alignment marks are expected to be located. As shown in FIG. 5, after the above etching process of the oxide film layer 12, a conductive material such as aluminum (Al) is sputtered over the oxide film layer 12 to form an Al wiring layer 16. When the Al wiring layer 16 is completed, such a recess as indicated in the figure comes out on the surface of the Al wiring layer 16, in correspondence with the position of each recess 14 formed by etching the oxide film layer 12 in part. Thus, these recesses can be used as alignment marks AM. As described above, the recess 14 plays a role as a base which defines the position of a designed or planned alignment mark AM. Therefore, for the purpose of simplifying the description, the recess 14 will be referred to as `base recess` hereinafter in this specification as well as in the recitation of claims as attached hereto.
In case of forming the base recess 14 for alignment mark AM by etching the oxide film layer 12 in part, its depth has to be carefully controlled, as shown in FIGS. 4 and 5, to avoid that the base recess 14 reaches the silicon substrate 10 by excess etching. Despite the control of this etching process, however, such excess etching might sometimes happen depending on unexpected change in the etching condition, for instance etching time, etching temperature, etchant, etc. Once such excess etching has happened, the base recess reaches the silicon substrate, so that the Al wiring layer 16 directly comes in contact with metallic silicon of the silicon substrate 10 when the Al wiring layer 16 is formed over the oxide film layer 12. Aluminum and silicon are essentially so active to each other that an Al--Si alloy is formed at the interface therebetween, if the Al wiring layer 16 is formed at a high temperature such as 500.degree. C. Therefore, according to the prior art method as described above, when aluminum wiring layer 16 and silicon substrate Si come in contact with each other under such high temperature condition, Al--Si chemical reaction rapidly and vigorously proceeds to produce a reaction layer 18, and the oxide film layer 12 is violently attacked and destroyed during this chemical reaction, as shown in FIG. 6, thereby the desired alignment mark AM being eliminated.